DAC vs. MAC • Most people familiar with discretionary access control (DAC) - Unix permission bits are an example - Might set a file private so only group friends can read it

Source URL: www.scs.stanford.edu

• Computer memory
• Bell–LaPadula model
• Covert channel
• Mandatory access control
• Classified information
• Htop
• CPU cache
• Access control
• Security clearance
• Security
• Computer security
• Computing

ColorSafe: Architectural Support for Debugging and Dynamically Avoiding Multi-variable Atomicity Violations Brandon Lucia† Luis Ceze†

Source URL: homes.cs.washington.edu

• Concurrency control
• Data management
• Memory management
• Debugging
• Software bug
• C dynamic memory allocation
• Pointer
• CPU cache
• MySQL
• Computing
• Data
• Transaction processing

Profiling R on a Contemporary Processor Shriram Sridharan Jignesh M. Patel University of Wisconsin–Madison

Source URL: quickstep.cs.wisc.edu

• Central processing unit
• Memory management
• Computer memory
• CPU cache
• Cache
• Compiler optimization
• Garbage collection
• Microarchitecture
• Cell
• Computer architecture
• Computer hardware
• Computing

Finding Concurrency Bugs with Context-Aware Communication Graphs Brandon Lucia Luis Ceze

Source URL: homes.cs.washington.edu

• Data
• Information
• Graph theory
• Data management
• Transaction processing
• Lock
• Serializability
• Graph
• CPU cache
• Computing
• Concurrency control
• Software bugs

ec2-sphinx-all-machines-new.tex

Source URL: pages.cs.wisc.edu

• Windows Server
• University of Cambridge Computer Laboratory
• Xen
• Hyper-V
• Amazon Elastic Compute Cloud
• Web server
• Virtual machine
• Cache
• CPU cache
• System software
• Computing
• Software

Tungsten Graphics Inc. MMThe DRM video memory manager

Source URL: web.archive.org

• Cache
• CPU cache
• Data buffer
• Accelerated Graphics Port
• X-Video Motion Compensation
• Multiple buffering
• Computer memory
• Computer hardware
• Computing

Appears in the Proceedings of 17th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’12) Architecture Support for Disciplined Approximate Programming Hadi Esmaeil

Source URL: homes.cs.washington.edu

• Computer engineering
• Instruction set architectures
• Microarchitecture
• Microprocessors
• Register file
• Instruction set
• DEC Alpha
• CPU cache
• Cell
• Computer architecture
• Computer hardware
• Central processing unit

Notebook specificationsLenovo W541 • OS: Windows 8.1 Enterprise 64 bit • CPU: Intel Core i7-4710MQ Quad Core (2,5 GHz, 6Mb Cache, Turbo 3,5GHz) • RAM: 8 GB (1x 8GB) 1600Mhz DDR3 memory (3 free slots)

Source URL: static.studiegids.tue.nl

Improving Data Access Efficiency by Using a Tagless Access Buffer (TAB) Alen Bardizbanyan Chalmers University of Technology

Source URL: www.cs.fsu.edu

• Central processing unit
• Computer architecture
• Whitespace
• CPU cache
• Cache
• Tab key
• C
• Memory hierarchy
• Translation lookaside buffer
• Computer memory
• Computing
• Computer hardware

Speculative Tag Access for Reduced Energy Dissipation in Set-Associative L1 Data Caches Alen Bardizbanyan† , Magnus Sj¨alander‡ , David Whalley‡ , and Per Larsson-Edefors† † Chalmers University of Technology,

Source URL: www.cs.fsu.edu

• Computer memory
• Cache
• CPU cache
• Translation lookaside buffer
• Lookup table
• Processor register
• Sum addressed decoder
• R8000
• Computer hardware
• Central processing unit
• Computing